Historically personal computers (PCs) have been designed around a model in which a general processor (CPU) processes all data that enters or leaves the system. Relatively simple Input/Output (I/O) Controllers are used to move data from external I/O data sources into memory for processing by the CPU, and to move the processed data from memory to external I/O data sinks. Virtually all I/O data enters or exits a platform as a stream of data units, whether as network data from the “cloud,” audio samples from a microphone or output to speakers, blocks of data from a disk, etc. The conventional I/O controllers simply move streams of native data units between I/O devices to main memory so that the CPU can manipulate the data.
PC architecture has recently been rapidly evolving to adapt to needs of mobile platforms, which are extremely sensitive to power efficiency. It has been demonstrated that there are many mobile usage models where it is more power efficient to implement specialized hardware functions (Accelerators) to process data, than it is to use employ a CPU. Most accelerators process I/O data as sequential streams of data units to and from memory. For example, in a common MPEG-2 Audio Layer III (MP3) playback scenario, an I/O controller is used to stream Ethernet frames that encapsulate an MP3 file from a remote source into a memory buffer. A first accelerator then may be employed to input the Ethernet Frames from memory and output MP3 encoded data to another memory buffer. A second accelerator may input MP3 data from memory and output audio samples back to yet another memory buffer. Finally another I/O controller may be employed to retrieve the audio samples from memory and output them to playback devices such as headphones.
A typical scenario for treating I/O is thus one in which a CPU configures an I/O controller to transfer I/O data into memory, configures one or more accelerators to process that data, and another I/O controller to output the data. In this scenario memory is used simply as a first-in first-out (FIFO) device for the data that is streamed between I/O controllers and accelerators. Another notable feature of current I/O controllers and accelerators is that each defines a unique method of moving data in and out of memory. This model requires a unique device program (driver) for each device in order to move data, as well as a higher level application to coordinate the drivers so that the data is passed between them in a first-in-first-out (FIFO) manner.
In present day architecture, the software configuration process of devices in an I/O pipeline may take place once for a given I/O operation, e.g., playing an MP3 file. However, device driver data management activity may occur at a frequency that is a function of the data rate and the size of FIFO buffers used to store data. Often FIFO buffers have been arranged with a small size in order to reduce the latency between devices, which results in an increase in the frequency of software activity. Recently new device or platform management has been developed to maximize system idle times to enable longer and deeper sleep states. To accomplish this, large hardware FIFO buffers may be added to I/O controllers so that they can burst large amounts of I/O data from main memory with a lower frequency, to minimize device driver data management activity, which may increase latency.